--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   22:12:24 09/04/2012
-- Design Name:   
-- Module Name:   /home/tom/StrathSat-R/strathsat-r/VHDL/sd_host/host_tb.vhd
-- Project Name:  sd_host
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: host
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
entity host_tb is
end host_tb;
 
architecture behavior of host_tb is
 
    -- Component Declaration for the Unit Under Test (UUT)
	component host
		port
		(
         Clk 				: in  	std_logic;
         Data 				: in  	std_logic_vector(7 downto 0);
         Sd_Cmd 			: inout  std_logic;
         Sd_Data 			: inout  std_logic;
			Sd_Clk			: out		std_logic;
			Cmd_Prev_Rx		: out		std_logic_vector(38 downto 0);
			Cmd_Prev_Tx		: out		std_logic_vector(5 downto 0)
       );
    end component;
    

   --Inputs
   signal Clk 				: std_logic := '0';
   signal Data 			: std_logic_vector(7 downto 0) := (others => '0');

	--BiDirs
   signal Sd_Cmd 			: std_logic;
   signal Sd_Data 		: std_logic;
	
	--Outputs
	signal Sd_Clk			: std_logic;
	signal Cmd_Prev_Rx	: std_logic_vector(38 downto 0);
	signal Cmd_Prev_Tx	: std_logic_vector(5 downto 0);

   -- Clock period definitions
   constant Clk_period 		: time := 10 ns;
   constant Sd_Clk_period 	: time := 10 ns;
 
BEGIN

--	stim : process
--	begin
	
--		Sd_Cmd <= 'Z';
--		wait for 200000 ns;
--		Sd_Cmd <= '0';
--		wait until rising_edge(Sd_Clk);
--		wait until rising_edge(Sd_Clk);
--		Sd_Cmd <= 'Z';
	
--	end process stim;
 
	-- Instantiate the Unit Under Test (UUT)
   uut: host 
		port map
		(
         Clk 			=> Clk,
         Data 			=> Data,
         Sd_Cmd 		=> Sd_Cmd,
         Sd_Data 		=> Sd_Data,
			Sd_Clk		=> Sd_Clk,
			Cmd_Prev_Rx	=> Cmd_Prev_Rx,
			Cmd_Prev_Tx	=> Cmd_Prev_Tx
		);

   -- Clock process definitions
   Clk_process : process
   begin
		Clk <= '0';
		wait for Clk_period/2;
		Clk <= '1';
		wait for Clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for Clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;
